1. Field of the Invention
The invention relates to a charge-coupled imager comprising a semiconductor body, a surface of which is provided with an imaging section comprising image elements arranged in a two-dimensional m×n pattern of m horizontal rows and n vertical columns and with a read-out section comprising a horizontal CCD channel beside the two-dimensional pattern for reading the pattern row by row, and vertical CCD channels within the pattern for transporting charge packets to the horizontal CCD channel per column of the image elements. The invention also relates to a camera fitted with such an imager.
2. Description of Related Art
An imager of the type described above is known, for example from patent application PCT/1897/01201 in the name of the applicant, which was published under number WO 98/17051.
As is known, charge-coupled imagers of the type referred to in the opening paragraph are used, inter alia, in electronic “still picture” cameras for capturing a radiation image and converting it into a large number of electric signals, whose size is a measure of the local light intensity. The signals can be stored on a magnetic memory, for example, for further processing, such as display on a monitor. Generally, the imager includes a color filter comprising three or more colors, which allows color imaging. Specific values for the size of the imager are, for example, 960 lines in the vertical direction with 1280 columns.
During operation, an image is projected onto the imaging section for an integration period. Once the integration period is over, the entry of light is blocked by means of a shutter and the charge packets can be read one by one via the horizontal CCD channel. In addition to this read-out mode, which is the normal-mode read-out mode, such imagers generally also comprise a possibility of a second read-out mode, for example for displaying an image on a monitor or an LCD viewer on the camera, in which 15 . . . 30 images are read per second, for example. In practice it has become apparent, however, that it is not easy to read an imager comprising 1 M image elements or pixels twenty-five times per second.
The aforementioned patent application WO 98/1705 discloses an imager having a vertical npn structure, in which a substrate is used which is of the same type as the n-type buried channel, which is separated from the CCD channels by the intermediate, thin p-type layer and can be used as a drain for electrons that need to be removed from the CCD channels. A memory section comprising 240 lines, for example, that is, one fourth of the total number of lines in the imaging section, is formed between the imaging section and the horizontal read-out section. The vertical sampling frequency (the number of samples per unit length in the vertical direction) can be reduced for the second read-out mode by dumping three out of every four lines of the imaging section via the substrate and storing only one line in the memory. As described in the aforesaid application, the non-selected lines can be dumped to the substrate in a simple manner by blocking the charge transport at the interface between the imaging section and the memory.
As the resolution increases, the read-out time will again be too long for generating the desired 15 . . . 30 images per second. Generally it is not possible to increase the clock frequency so as to read more signals per unit time, because this would automatically lead to an unacceptably low signal-to-noise ratio. It is not advisable to just reduce the number of signals per line, on account of the fixed length, and thus the fixed number of cells to be read, of the horizontal register.